1. Field
Various embodiments of the present invention relate to a memory device.
2. Description of the Related Art
In general, memory devices activate a row (i.e., a word line) selected by a row address when an active command is inputted from a memory controller, and access (e.g., read or write) a memory cell coupled to a column (i.e., a bit line) selected by a column address among memory cells coupled to the activated row when a data write command or data read command is inputted.
The memory devices include a cell array in which a plurality of memory cells are arranged in rows and columns, and a group of a cell array, which corresponds to a bank address, is referred to as a memory bank (hereafter, referred to as a bank). The memory devices include a plurality of banks, and the banks may be divided into bank groups each including a predetermined number of banks. The memory devices perform an operation corresponding to a write or read command on the basis of a bank group.
FIG. 1A is a diagram illustrating a conventional memory device.
Referring to FIG. 1A, the memory device includes a command/address control unit 110 and first to fourth bank groups BG0 to BG3. Each of the bank groups BG0 to BG3 includes four banks BK0 to BK15.
The command/address control unit 110 transmits a column command signal RD/WT and a column address signal CADD<0:5> having a multiple bits to the respective bank groups BG0 to BG3 through lines BUS<0:7>. When the column command signal RD/WT and the column address signal CADD<0:5> are received, each of the bank groups BG0 to BG3 activates a column select signal by decoding the column command signal RD/WT and the column address signal CADD<0:5>, and write data to a memory cell coupled to a column corresponding to the activated column select signal or read data from the memory cell.
FIG. 1B is a timing diagram for describing an operation of the memory device illustrated in FIG. 1A.
When column commands R1 to R4 and W1 to W4 are successively inputted to the memory device, the column command signals RD and WT are successively activated, and the values of the column address signals CADD1 to CADD8 inputted with the column commands may be maintained from when a corresponding column command signal RD or WT is activated to when the next column command signal is activated. The column commands R1 to R4 correspond to the column address signals CADD1 to CADD4, and the column commands W1 to W4 correspond to the column address signals CADD5 to CADD8, respectively.
When the column commands are inputted at each clock cycle as illustrated in FIG. 1B, the respective column address signals CADD1 to CADD8 are maintained for one clock cycle. With the increase in operating frequency of the memory device, one cycle tCK of a clock CK has shortened. The increase of the clock frequency reduces the widths of the command signals RD and WT and the column address signal CADD<0:5>, thereby causing the reduction in a timing margin.
In order to prevent the timing margin from reducing, the memory device of FIG. 1A may include separate lines, which correspond to the respective bank groups, for transmitting the command signals WT and RD and the column address signal CADD<0:5> to the respective bank groups. As such, when the command/address signal transmission lines are provided for the respective bank groups, the column address signals may be maintained until the next bank group is accessed after a certain bank group is accessed, in case where the same bank group is not successively accessed. Thus, the timing margin may be increased. However, since the number of lines for transmitting the command signals and the column address signal is significantly increased as the number of bank groups is increased, the circuit area of the memory device inevitably increases.